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Convex optimization in circuit design

Convex Optimization in circuit design

Group-5

Abstract— This is a brief report on optimization techniques

used in circuit design. We first discuss about the basic terminol-

ogy/concepts required to formulate the optimization problem.

We consider the simple case of gate scaling problem, its variants

and also look at a dynamic programming approach to solve the

optimization problem. We also look at a statistical approach

of formulating the problem in section 2. In the third section

we discuss supply and threshold voltage optimization, a joint

optimization of delay and power. At the end we discuss two

examples from the boyd extra exercises one being related to

vlsi circuit design and the other relates to non-linear circuit

optimization. Keywords: Gate scaling, path delay, Geometric

programming, posynomials

I. BASIC TERMINOLOGY

A. Introduction & Motivation

Consider a Combinational Logic circuit, i.e, the circuit

does not have any memory. These have a variety of

applications and are also a part of the sequential logic

circuits which have Combinational + Memory block. Mostly

there are different kinds of Gates like OR, AND, NAND”,

etc whose fundamental component is a Transistor. These

transistors help drive any circuit. But as they occupy area

and consume power, it becomes important to somehow

optimize these. When we think of a circuit, we want it to be

very fast. Hence optimizing with respect to delay becomes

one of the utmost priority.

B. RC Gate delay

Any transistor can be modelled using Resistors and

Capacitors. Hence we would like to see how the delay exists

because of these components. As we have a combination of

several transistors, each block would be having a Capacitive

load towards the end which is basically the input capacitance

of the next gate. We denote that be C(load). There will

be intrinsic capacitances and resistances in both the pull

up and pull down networks. The gates are usually sized

in such a way so as to make the HIGH-LOW delay same

as LOW-HIGH delay. Along with these there will be input

gate capacitances. Because of scaling of gates, lets say by

a factor x, then the Capacitance C becomes Cx and the

Resistance R becomes R/x.

RC Gate delay Model:

Input and intrinsic capacitances, driving resistance”,

load capacitance:

Cini = C̄

in

i xi, C

int

i = C̄

int

i xi (1)

Ri = R̄i/xi, C

L

i = Σj∈FO(i)C

in

j (2)

RC Gate Delay:

Di = 0.69Rin(C

L

i + C

int

i ) (3)

= 0.69(R̄iC̄

in

i + (R̄i/xi)Σj∈FO(i)C

in

j ) (4)

Di are posynomials (of scale factors)

C. Path delay

Delay is additive. As the signal is supposed to pass

through multiple gates, the delays of each gate add up.

Hence, other than just optimizing the individual gate delays”,

we have to optimize the entire path delay too.

Path delay model:

Delay of a path = sum of delays of gates on path

Delay of a path is also a posynomial.

D. Area and Power

In real life situations we will have a lot of constraints.

Two of the most important constraints being Area and

Power. We cant consume a lot of area because otherwise the

size of the everyday devices we use will be very big. Power

consumption is important as it directly related to Energy

and we have to keep that in check. Area: Considering the

scaling, the total area would be the weighted sum of each

individual areas.

Total circuit area

A = x1Ā1 + …+ xnĀn (5)

Power: Theres static power and Dynamic power. Static

power arises due to leakages and this happens when it

is in ON state. Dynamic power constitutes the power

being consumer whenever theres a switching action taking

place. Hence dynamic power is dependent on the switching

frequency.

Total Power:

P = Pdyn + Pstat (6)

Dynamic Power:

Pdyn =

n∑

i=1

fi(C

L

i + C

int

i )V

2

dd (7)

where fi is the gate switching frequency

Static Power:

Pstat =

n∑

i=1

xiI

leak

i Vdd (8)

I leaki is the leakage current (average over input states) of

unit scaled gate

Here A and P are posynomials.

II. GATE SCALING PROBLEM

A. The basic scaling problem

Now we formulate a basic gate scaling problem:

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1) Choose the scale factors to give minimum delay

2) Subject to limits on the total area and power

Optimization problem is given by:

minimize D

subject to P ≤ Pmax, A ≤ Amax

1 ≤ xi, i = 1, …, n

(9)

• Pmax and Amax are given limits on the total power and

area respectively

• Variables of optimization are the scale factors x1 , x2

“,. . . . . . xn

The optimal solution to the above GP gives the fastest

circuit with given area and power budgets. Clock frequency

maximization can be thought of an extension to the above

optimization problem. Now we formulate it as maximising

the circuit clock frequency fclk instead of the circuit delay”,

as the objective

Timing Requirement : fclkD0.8 ≤ 1

(20% margin for flip-flop delay, setup time, clock skew)

Optimization problem is given by:

maximize fclk

subject to P ≤ Pmax, A ≤ Amax”,

fclkD

0.8

≤ 1

1 ≤ xi, i = 1, …, n

(10)

Here variables of optimization are x1 , x2″,. . . . . . xn and fclk

B. A dynamic programming approach for the GP

Let us consider solving the optimization problem where

we would like to minimise the total circuit delay. We know

that this is the maximum of all possible path delays from

input to output. This can be computed using the following

recursion:

Ti = max(Tj) +Di (11)

where Di is the delay of the ith gate and Tj is the circuit

delay calculated until the jth gate, j ∈ FI(i). The total

circuit delay can be calculated using the following equation:

D = max(Ti|i an output gate) (12)

This can again be framed as an optimization problem where

we try to minimize delay for every particular gate(solving the

sub-problems). The problem can be formulated as follows:

minimize T̄

subject to T̄j ≤ T̄ for j an output gate”,

T̄j +Di ≤ T̄ifor j ∈ FI(i)

P ≤ Pmax, A ≤ Amax”,

1 ≤ xi, i = 1, …, n

(13)

In this case, we might have introduced many extra variables.

But the overall constraint matrix will be sparse because at a

given gate, the constraint matrix will have non-zero entries

only at the fan-in of that particular gate. This sparsity can

be exploited by many GP solvers to improve its efficiency.

C. Statistical approach

This sub section deals with how statistical variations in

different parameters of a digital circuit can be approximated

as a GP or a GGP problem. We start off by assuming that the

delay, power dissipated in equation (9) are random variables

with a very less variance from their mean. Here we consider

how the statistical variations in the Vth of a gate affects

all the parameters. We also assume that the distribution

followed by Vth is gaussian. Since we need to remove the

”randomness” in our constraints and the objective function”,

we replace the random variables with their expectation.

For the sake of simplicity, we assume that all the random

variables are independent. So the new optimization problem

can be formulated as follows:

minimize E(D)

subject to E(P ) ≤ Pmax, A ≤ Amax

1 ≤ xi, i = 1, …, n

(14)

1) An expression for E(P ): We know that the total

power is sum of all individual gate powers individual gate

powers.The following equation relates the standard deviation

of threshold voltage and the gate scaling. This is known as

Pelgram’s model.

σVth = σ̄Vth/

x (15)

where σ

Vth

is the standard deviation of unit scaled gate We

also know that the leakage current varies with Vth varies as

follows:

Ileak α e

−Vth

V0 (16)

where V0 is a constant.

One observation that can be made from pelgram’s model

is that as the gate scaling increases, the variance reduces.

Also, we assume that Vth follows gaussian distribution. This

implies that Ileak follows log-normal distribution.

=⇒ E(Ileak) = I0e

σ̄2Vth

2V 20 x (17)

From the above equation, it is clear that the actual leakage

current is higher than the nominal leakage current and also

decreases with increase in the scaling factor. The above

exponential can be approximated as a posynomial for a very

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large value of a which is given by the following expression

e

σ̄2Vth

2V 20 x = (1 +

σ̄2Vth

2V 20 xa

)

a

(18)

So, the static power can now be approximated as a polyno-

mial by substituting (18) in (17) and substituting this in (8).

This was easier because it was sum of independent random

variables.

2) An expression for E(D): This is a complicated prob-

lem because D is the maximum of n independent random

variables. It is a difficult problem to derive a closed form

posynomial expression for E(D). We again start working

our way through this by considering the alpha power law

model which relates the delay of a gate with its Vth which

is as follows:

D = k

Vdd

(Vdd − Vth)α

(19)

The standard deviation of D can also be approximated as

follows:

σ =

ασ̄Vth

Vdd − Vth

x−1/2D (20)

Since we cannot get a closed form posynomial for the

maximum of all possible path delays, we apply a heuristic so

that it gets converted to a GP. The heuristic or the ”surrogate”

delay model is as follows:

D̃i = Di + κiσi (21)

where Di is the posynomial which we calculate using (4)

for every gate and σi is the standard deviation associated

with the ith gate. Intuitively, this modeling is same as

approximating the randomness associated with every delay

as some value which is κi standard deviations away from

whatever we calculate using (4). This is again a posynomial

in the scaling factors (from (20)”,(4)). So, in the optimization

problem in (9), we calculate D using this surrogate delay

model and the power will be replaced by E(P ). This again is

a GGP problem and as per the results in the paper, statistical

modeling performs better than non-statistical approach.

III. SUPPLY AND THRESHOLD VOLTAGE OPTIMIZATION

A. Posynomial Gate Delay Model

Here we model the delay of a gate as a function of

threshold voltage, power supply voltage, scale factor, load

capacitance and input signal transition time by making use

of the result from alpha power model given by

Di =

Vdd”,i

(Vdd”,i − Vth”,i)α

D̃i(x) (22)

The generalized posynomial approximation for D is given

by

D̂i = V

1−α

dd”,i (1 +

Vth”,i

Vdd”,i

+ …+ (

Vth”,i

Vdd”,i

)5)D̃i(x) (23)

error under 1% for Vdd”,i ≥ 2Vth”,i, 1.3 ≤ α ≤ 2

B. Posynomial Power Model

The total dynamic power dissipated in terms of supply

voltages for the gates is given by

Pdyn =

n∑

i=1

fi(C

L

i + C

int

i )V

2

dd”,i (24)

similarly average static power in terms of leakage current

and supply voltages is given by

Pstat =

n∑

i=1

xiĪi

leak

Vdd”,i (25)

Ī leaki ∝ exp

−(Vth”,i−γVdd”,i)

V0 (26)

It is point to be noted that Pstat by itself cannot be

approximated well by a generalized posynomial over a

large range of Vdd, Vth where as the total power can be

approximated well by a generalized posynomial

C. Joint optimization of gate sizes

A joint optimization is formulated by choosing supply

voltages, threshold voltages and scale factors as design

variables. The GP is formulated as

minimize D

subject to P ≤ Pmax, A ≤ Amax”,

V minth ≤ Vth”,t ≤ V maxth , i = 1, …, n

V mindd ≤ Vdd”,t ≤ V maxdd , i = 1, …, n

other constraints ….

(27)

IV. BLEND DESIGN PROBLEM

This is actually an interesting problem which we found in

the boyd extra exercises book where we try to solve the GP

problem in which we do not explicitly know the expressions

of P”,D”,A but we only know that they are posynomials. We

are given k design specifications w1, w2, …, wk ∈ Rn where

n is the number of gates in our circuit. We are also given

the total power, delay and area of the k design specifications.

Now, the task is to find an optimal ”blend” of these designs

”w” such that P”,D”,A are less than a particular maximum

value.

P”,D”,A are posynomials, we can do a change of variables

which is w = ex such that there will be a summation of

variables in the exponent. Also, we can consider the log of

sum of these exponents (each exponent has a linear combi-

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nation of x′is) which is a convex function. By the definition

of convexity, logP (w) ≤ Σi=ki=1θilogP (wi) similarly for both

D(w), A(w). We impose the constraint on this upper bound.

Therefore, the constraints transform as follows:

Σi=ki=1θilog(P (wi)) ≤ log(Pmax)

Σi=ki=1θilog(D(wi)) ≤ log(Dmax)

Σi=ki=1θilog(A(wi)) ≤ log(Amax)

Σi=ki=1θi = 1, θi ≥ 0

(28)

So the problem can be finding θ such that constraints in (28)

are satisfied and woptimal = πki=1w

θi

i

V. NON LINEAR CIRCUIT OPTIMIZATION

As an electrical engineer, we come across many circuits

and many methods to analyse them. In almost all the methods

we end up solving the nodal analysis and mesh analysis

which in many cases drops down to many equations and

many parameters. To solve these equations convex optimisa-

tion becomes very handy if we can formulate our problem

of non-linear circuit analysis into a convex optimisation

problem.

A. The problem

Let us consider a circuit with ’b’ two-terminal devices

which can be a resistor, capacitor, inductor, voltage source”,

diode etc, we need to compute several sets of physical

quantities that characterize the circuit operation. The vector

of branch currents is i ∈ Rb, where ij is the current owing

through device j. The vector of node potentials is e ∈ Rn”,

where ek is the potential of node k with respect to the ground

node.

As current is conserved at each node (KCL) which can be

mathematically expressed as Ai = 0, and voltage across each

branch is the difference between the potentials at the nodes

(KV) which can be mathematically expressed as v = AT e”,

where A ∈ Rnxb where A is a reduced incidence matrix

which describes circuit topology.

Akj =



-1, branch j enters node k

1 branch j leaves node k

0 otherwise

Now, we can even relate branch voltages and currents as :

vj = φj(ij), j = 1, …., b

where φj is a given function that depends on the type of

device j.

a) If device j is a resistor with resistance Rj > 0, then

φj(ij) = Rjij

b) If device j is a voltage source with voltage vj > 0 and

internal resistance rj > 0″,then

φj(ij) = Vj + rjij

c) if device j is a diode, then

φj(ij) = VT log(1 + ij/IS)

where, VT and IS are positive constants.

B. Formulation

To formulate for problem as a convex optimisation prob-

lem, we consider a function

ψ(i1, …ib) =

b∑

j=1

∫ ij

φj(uj)duj

which is a continuos, non-decreasing convex function in ’ij’”,

the derivative of this will be

5ψ(i1, …ib) = (φ1(i1), ….φb(ib))

Thus we can formulate our convex optimisation problem as

minimize ψ(i)

subject to Ai = 0, i ∈ Rb”,

5 ψ(i) + v +ATυ = 0

(29)

Here, υ is a dual variable associated with the constraint

Ai = 0. Defining υ = 5ψ(i) and e = −υ, we get our final

optimisation problem as

minimize ψ(i)

subject to Ai = 0, i ∈ Rb”,

AT e = υ

υj = φj(ij)

(30)

If we observe , These constraints are exactly ours circuit

equations and φ’s are termed as content functions.

Let’s solve this with an example:

Consider the circuit shown in the diagram below. Device 1

is a voltage source with parameters V1 = 1000, r1 = 1.

Devices 2 and 5 are resistors with resistance R2 = 1000″,

and R5 = 100 respectively. Devices 3 and 4 are identical

diodes with parameters VT = 26, IS = 1. (The units are

mV “,mA, and ω) The nodes are labeled N1, N2, andN3 the

ground node is at the bottom. The incidence matrix A is

Computing the content function of each

• Resistor ∫ i

rudu = 0.5ri2 (31)

• Voltage Source∫ i

V + rudu = V i+ 0.5ri2 (32)

• Diode

VT

∫ i

log(1+

u

Is

)du = VT Is((1+

i

Is

)log(1+

i

Is

)− i

Is

)

(33)

Now, Our final optimisation problem will be

minimize V1i1 + 0.5Σj∈(1″,2″,5)Rj(ij)2+

Σj∈(3″,4)VT Is((1 +

ij

Is

)log(1 +

ij

Is

)− ij

Is

)

subject to Ai = 0

(34)

VI. REFERENCES

• ”Geometric Programming for Circuit Design” slides by

Stephen Boyd et.al

• ”Digital Circuit Optimization via Geometric

Programming” by Stephen Boyd et.al

• Additional exercises for convex optimization by Stephen

Boyd et.al

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